hi-8050/51, hi-8150/51 cmos high voltage display driver general description the hi-8050, hi-8051, hi-8150 and hi-8151 are cmos integrated circuits designed for high voltage lcd display drive applications. the hi-8050 & hi-8051 have ttl logic inputs whereas the hi-8150 & hi-8151 have cmos logic inputs. they drive up to 38 segments at voltages between +5 and -30 volts. the optional voltage converter on the hi-8050 & hi-8150 can be used to generate the negative display drive voltage. all products have test inputs to facilitate opens and shorts testing as well as automatic blanking of the display if the +5v power is lost. the hi-8050 and hi-8150 are designed to replace the hi-8010 and hi-8020 devices in all 5 volt applications. they offer significantly enhanced esd protection along with a considerably faster serial input data rate. the data is serially clocked into the device on the negative edge of the clock and latched in parallel to the segment outputs on the high to low transition of the load input. serial output data changes on the positive edge of the clock allowing the cascading of multiple drivers for larger dis- plays. the device layout supports all previous pinouts of the hi-8010/hi-8020 products. in addition, new technology and features afford new packaging options. consult your holt sales representative to explore the possibilities. dichroic liquid crystal displays standard liquid crystal displays 5 volt serial data to parallel high voltage mems drivers applications 4 mhz serial input data rate 38 segment outputs cascadable 5 volt inputs translated to 35 volts test pins allow hardware all "on", all "off" or alternating monitors 5 volt supply and forces all segments to "off" condition if lost negative voltage converter available on-chip cmos low power military processing available features pad configuration (top view) functional block diagram oscillator divider voltage translator high voltage buffer 38 stage shift register 38 bit latch voltage translators high voltage drivers bpout 38 segments din ld bpin bposc cl cs 8020opt data in clk le dout38 dout32 dout30 control logic february 2003 bpin bposc vdd n/c convosc convout vee s37 s38 s1 s2 s3 s4 s5 s6 s7 s27 s26 s25 s24 s23 s22 s21 s20 dout38 dout32 dout30 t2 t1 n/c bpout n/c n/c din ld vss s36 s35 s34 s33 s32 s31 s30 s29 s28 cl cs 8020opt n/c s8 s9 s10 s11 s12 s13 s14 n/c s15 s16 s17 s18 s19 n/c n/c hi-8050pqi hi-8150pqi hi-8050pqt & HI-8150PQT 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 64 pin plastic pqfp (see page 6 for hi-8051 & hi-8151pin configurations) holt integrated circuits www.holtic.com (ds8050 rev. d) 02/03
hi-8050/51, hi-8150/51 pin description table vss power 0 volts logic input open or high logic level selects the hi-8010/hi-8110 / logic. a low selects the hi-8020/hi-8120 logic (hi-8050 & hi-8150 only) logic input chip select - active low logic input serial data input clock - active low ld logic input latches data in shift register to the segment outputs - active high din logic input serial input data to the shift register bpin input backplane frequency input. either driven from an external source or connected to bposc and an external resistor and capacitor. bposc output internal oscillator pin. connected to bpin and an external resistor and capacitor vdd power +5v 5%, positive voltage of the backplane and segments convosc input used in conjunction with convout to generate the negative vee voltage on-chip (hi-8050 & hi-8150 only). convout output used in conjunction with convosc to generate the negative vee voltage on-chip (hi-8050 & hi-8150 only). vee power negative voltage of the backplane and segments - between vss and vdd - 35v s1 to s38 output segment outputs to lcd display bpout output backplane output to lcd display (see figure 3 for cascading drivers) t1 logic input used in conjunction with t2 to control display mode. normal mode is logic low. t2 logic input used in conjunction with t1 to control display mode. normal mode is logic low. dout30 output logic output from the 30th bit of the shift register. use for pattern verification or as the din of the next cascaded driver (hi-8050 & hi-8150 only). dout32 output dout38 output signal function description 8020opt cl cs cs cl logic output from the 32nd bit of the shift register. use for pattern verification or as the din of the next cascaded driver (hi-8050 & hi-8150 only). logic output from the 38th bit of the shift register. use for pattern verification or as the din of the next cascaded driver. holt integrated circuits 2
hi-8050/51, hi-8150/51 functional description input logic bposc and bpin the data is clocked into a serial shift register from the din in- put on the negative edge of while is held low. ld is normally held low and pulsed high only when data from the shift register is parallel latched to the segment outputs. must be low when ld is pulsed. the latches are transparent while ld is high. a logic "1" in the shift register causes the corresponding segment output to be out of phase with the bp output. all four logic inputs are ttl compatible on the hi-8050/51and cmos compatible on the hi-8150/51. the user has the option of creating the backplane frequency internally or providing a signal from an external source. for an internal oscillator, bpin and bposc are connected to- gether and the appropriate r & c combination is applied as shown in figure 1. the resulting backplane frequency is ap- proximately: f = 1 . (r = 220k , c = 220pf, f 100hz) the value of the resistor must be greater than 30k . alternatively, bposc is left open and an external backplane signal of the desired frequency is applied to the bpin input. cl cs cs bp bp vee & negative voltage converter vee can be connected to a negative power supply. alterna- tively, the hi-8050 & hi-8150 have the option of generating the vee voltage with a built-in -25 volt negative voltage con- verter (see figure 2). when not used, the open convosc pin is detected and all power consuming circuitry is dis- abled. the converter will survive a short between two seg- ments and still maintain a vee voltage of -20v. dout the dout30, dout32, and dout38 pins are available for cascading devices to drive more segments (see figure 3) and for verifying the integrity of the shift register data. the outputs can drive 2 ttl loads. they change on the positive edge of . cl automatic segments off test inputs a threshold device detects when the 5v supply is below ap- proximately 1v and forces all the segments and the backplane to the same level. this feature is used to discharge the vee capacitor when the 5v power is switched off, to prolong the life of the lcd display. the and inputs function the same as the hi-8010 and hi-8110 product (see figure 5) if this pin is left open or held high. if held low, the two pins function the same as the hi-8020 and hi-8120 product (see figure 6). this input is available only on the hi-8050 (ttl) and hi-8150 (cmos) products. the test functions available are: 0 0 normal 0 1 all off 1 0 all on 1 1 alternating on/off segments the test inputs must be tied to the appropriate logic level for correct circuit operation. both test inputs are ttl compatible on the hi-8050/51 and cmos compatible on the hi-8150/51. 8020opt cl cs t2 t1 display ode m 256 rc figure 2. optional voltage converter convosc convout vee control osc v dd 68k in5818, in5819 330h 10f v dd v ss v ss sense r figure 1. internal oscillator circuit bpin to backplane translator and driver 256 r c v ss bposc c r q v dd holt integrated circuits 3
figure 5. hi-8010/hi-8110 & logic ( = open or high) cl cs 8020opt segments segments segments back plane din cs din cl ld do bpin bpout bposc cs din cl ld do bpin bposc cs din cl ld do bpin bposc cs cl ld bpout bpout r c figure 4. offset measurement bpout 1500pf 1f 1m 1m 1f 1f 1f 1m 1m 360pf seg v os n figure 7. timing diagram 38 stage shift register data in clk din cl cs dout din cl cs 38 stage shift register data in clk dout figure 3. rc oscillator and cascaded devices figure 6. hi-8020/hi-8120 & logic ( = low) cl cs 8020opt t csh t css t ds t dh t cl t cdo t ls t lw t csl t lcs cl input din input cs input ld input dout output valid valid valid valid valid t ls hi-8050/51, hi-8150/51 holt integrated circuits 4
hi-8050/51, hi-8150/51 absolute maximum ratings note: stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc electrical characteristics vdd = 5v 5%, vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). voltages referenced to vss = 0v supply voltage vdd ..........................0v to 7v vee................vdd-35v to 0v voltage at any input, except bpin..-0.3v to vdd+0.3v voltage at bpin input ..............vdd-35v to vdd+0.3v dc current per input pin .....................................10 ma power dissipation............................................500 mw operating temperature range(industrial) ....... -40c to +85c (hi-temp/mil) ..... -55c to +125c storage temperature ..................................... -65c to +125c solder temperature (leads) ..................... +280c for 10 sec. (package) ........................................ +220c junction temperature, tj ... ....................................... +175c parameter symbol condition min typ max units operating voltage vdd 3.0 7.0 v supply current: (converter off, f = 0hz) idd static, no load 200 a iee static, no load 120 a input low voltage, hi-8050/51 only (except bpin) vil logic inputs 0 0.8 v input high voltage, hi-8050/51 only (except bpin) vih logic inputs 2 vdd v input low voltage, bpin vilx vee 0.6 vdd v input high voltage, bpin vihx 0.8 vdd vdd v input current (except t1 & t2) iin vin = 0v to 5v 100 na input current (t1 & t2) iin vin = 0v to 5v 10 input capacitance (guaranteed, not tested) ci 10 pf segment output impedance rseg il = 10a 10 15 k backplane output impedance rbp il = 10a @ 25c 450 600 data out current: source current idoh voh = 4.5 -3.0 ma sink current idol vol = 0.4 3.2 ma voltage converter: @ no load vee see fig. 2 -22 -21.5 -21 v (vdd - vss = 5v, ta = 25c) @ 0.1ma load idd see fig. 2 1.8 ma @ 10k load vee see fig. 2 -20 v offset voltage (guaranteed, not tested) vos see fig. 4 25 mv bp ttl ttl input low voltage, hi-8150/51 only (except bpin) vil logic inputs 0 0.3 vdd v input high voltage, hi-8150/51 only (except bpin) vih logic inputs 0.7 vdd vdd v a cmos cmos 1 2 c c holt integrated circuits 5
s7 s8 s9 s10 s11 s12 s13 s14 vee s15 s16 s17 s18 1 2 3 4 5 6 7 8 9 10 11 12 13 ld din bpin bposc vdd s37 s38 s1 s2 s3 s4 s5 s6 52 51 50 49 48 47 46 45 44 43 42 41 40 cl cs vss s36 s35 s34 s33 s32 s31 s30 s29 s28 s27 s26 s25 s24 s23 s22 s21 s20 dout 38 n/c t2 t1 bpout s19 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 pin plastic pqfp parameter symbol vdd min typ max units clock period non-cascaded t 5v 250 ns cascaded t 5v 500 ns clock pulse width non-cascaded t 5v 125 ns cascaded t 5v 250 ns data in - setup t 5v 50 ns data in - hold t 5v 80 ns chip select - setup to clock t 5v 100 ns chip select - hold to clock t 5v 120 ns load - setup to clock t 5v 120 ns chip select - setup to load t 5v 0 ns load pulse width t 5v 130 ns chip select - hold to load t 5v 120 ns data out valid, from clock t 5v 170 ns cl cl cw cw ds dh css csh csl lw lcs cdo ls hi-8050/51, hi-8150/51 hi-8051 & hi-8151 pin configurations (see page 1 for hi-8050 & hi-8150 pin configurations) ac electrical characteristics (see figure 7) vdd = , vee = -25v, vss = 0v, ta = operating temperature range (unless otherwise specified). 5v 5% hi-8051pqi hi-8151pqi hi-8051pqt & hi-8151pqt holt integrated circuits 6
hi-8050/51, hi-8150/51 ordering information part temperature burn lead number range flow in finish i -40c to + 85c i no solder t -55c to +125c t no solder part package number description 0 64 pin plastic thin flat quad pack (pqfp) 1 52 pin plastic quad flat pack ( pqfp) part logic # number input levels segments hi-805 ttl 38 hi-815 cmos 38 hi - 805xpqx holt integrated circuits 7
.079 .002 (2.00 .05) .520 .010 (13.2 .25) sq. .354 .008 (9.00 .20) sq. .063 max. (1.60 max. .0157 bsc (0.40 bsc) .007 .004 (0.18 .05) .024 +.006/-.004 (0.60 +.15/-.10) .008 r typ. (0.20 r typ. .055 .002 (1.4 .05) .008 r typ. (0.20 r typ.) .004 .002 (0.10 .05) .276 .004 (7.00 .10) sq. see detail a see detail a detail a .010 to .020 (0.25 to 0.50) package type: da etail .096 max. (2.45 max. ) .008 r typ. (0.20 r typ.) .012 .002 (.30 .05) .0256 bsc (0.65 bsc) .012 r . typ (0.30 r .) typ .035 +.006/-.004 (.88 +.15/-.10) .394 .004 (10.00 .10) sq. holt integrated circuits 8 package type: 52pqs 52 pin plastic quad flat pack (pqfp) package type: 64ptqs 64 pin plastic thin quad flat pack (pqfp) hi-8050/51, hi-8150/51 package dimensions inches (millimeters)
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